Integrated circuit (IC) manufacturers rigorously test their ICs to guarantee functionality, performance, and compliance with data sheet specifications and various industry standards. In many instances, IC manufacturers employ automated test equipment (ATE) to perform the various tests. An ATE's test capabilities are generally limited by operating frequency, number of input/output (I/O) channels/terminals available, and various modules used for testing features of an IC. As technology evolves, higher performing ICs are being manufactured, for example, faster and functionally more complex ICs including hundreds of I/O terminals which often exceed the ATE capabilities. In such instances, the IC manufacturer may be forced to upgrade to a more expensive ATE, or relying on a sub-optimal testing environment.
In an example, a programmable logic device (PLD) is well-known type of an IC that can be programmed to perform a specified logic function. The PLD can be configured to perform a logic function based on configuration data uploaded during the configuration cycle of the PLD. One type of PLD is a field programmable gate array (FPGA). Advancements in FPGA development the past few years have made them very valuable devices for system development in highly integrated systems. An advanced FPGA device typically has a high operating frequency and hundreds of I/O terminals that may be coupled to a printed circuit board (PCB) as a part of a system. Testing these advanced FPGA's including hundreds of I/O terminals has been a very challenging task due in part to the ATE limitation in terms of the number of I/O channels available.
Therefore, a need exists for a method and apparatus for testing an IC including numerous I/O terminals that complements ATE capabilities, and provides information regarding performance and pass/fail criteria of the IC device.